Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 55

Latch clock-gating control Latch clock-gating control

Pipeline stage clock-gating

D-Cache
Decoder

“Extended” latches

FIGURE 4.4: Deterministic Clock Gating. Pipeline latches and pipeline stages that can be clock-gated
are shown shaded.Adapted from [ 152 ].

The Fetch and Decode stages and their latches are never clock-gated since instructions
are needed almost every cycle. Decode stage information (i.e., number of decoded instructions)
determines the glock gating of the issue latches (L3). 2 Unfortunately, there is no time to gate
the L2 latches by the time this information is available. Although the Rename stage could be
gated, it is also left clocked.
Decode stage information can be used to clock-gate up to the Issue stage. There, in-
structions are buffered in an instruction queue. Further power optimizations for the instruction
queue are presented in Section 4.5. Every cycle, a decision is made anew by the scheduler on
which instructions to forward to the next stage for execution. This information, passed via the
“extended” always-clocked latches, can now be used to clock-gate all the subsequent pipeline
latches, as well as the execution units, the data cache—in particular its ports—and the result-bus
drivers.
Issue-stage information comes too late to clock-gate the Issue-latches themselves (L4)
or the Register Read stage, but on time to clock-gate the rest of the latches (L5, L6, L7, and
L8). Similarly, execution units can be clock-gated with Issue-stage information. At issue time,
we know what functional unit is needed and by when.
Load/store instructions determine the clock gating for the data cache. Depending on the
number of memory accesses during a cycle, data cache ports—essentially the dynamic logic
of the decoder and its wordline drivers—are clock gated. Although this is a straightforward

2 A similar concept but at a finer granularity is used to clock gate the unused width of the datapath; this concept is
presented separately in Section 4.3.