Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 54

GUARDED EVALUATION of F

Combinatorial Circuit

Combinatorial Circuit

Guard Latches

x

x

F

F

output

output

S

S

FIGURE 4.3: Guarded evaluation: a signal S determines when the output x of a set of gates F is a don't
care for the generation of the final output. S can be used to gate the inputs to F, effectively shutting
down F when it is not needed for the evaluation of the final output. Adapted from [ 218 ].

4.2.3 Deterministic Clock Gating
At a still higher level, at the level of processor core, deterministic clock gating—gating the
clock to processor structures when they are known to be idle—provides noticeable power sav-
ings without performance loss. It safely improves EDP by not compromising performance
[ 152 ]. With perfect clock gating, power savings (over the unoptimized design) are propor-
tional to the average part of the hardware that a program leaves idle during each cycle of its
execution.
Although the idea is straightforward and used in actual processors from early on [ 58 ],
its application on a superscalar pipeline was not published until 2003. In the mean time, a few
predictive clock-gating techniques had already been proposed (we will discuss some of those
later in this chapter). Li, Bhunia, Chen, Vijaykumar, and Roy give a detailed description of
deterministic clock gating in a superscalar pipeline [ 152 ]. They consider a high-performance
implementation using dynamic domino logic for speed. This means that—besides latches—the
pipeline stages themselves must be clock-gated. As per our discussion above, it is not enough
to stop their inputs from changing; their clock must be stopped as well.
In both cases, the deterministic nature of clock gating stems from the ability to deduce
a few cycles in advance the idleness (or use) of a latch or a pipeline stage. Once a decision to
stop the clock is made, it is carried via additional (always clocked) latches to the correct stage or
latch and delivered at the right cycle. Clock gating control proceeds down the pipeline similarly
to a bubble.
Figure 4.4 shows the 8-stage, superscalar, pipeline used by Li et al. in their study [ 152 ].
The pipeline stages and latches that can be deterministically clock-gated are shown shaded.
The decision to gate a stage (or the latches of a stage) must be taken at a previous pipeline
stage—i.e., well in advance of the cycle that is gated.