Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 53

in out

in out

Combinatorial
circuit clk

clk clk

cond

cond

in out

Combinatorial
circuit

clk
cond

in

out

clk
cond

clk

clk

FIGURE 4.2: Automatic clock gating transformations at the RTL level.

4.2.2 Precomputation and Guarded Evaluation
At a coarser granularity, at the level of a logic block, systematic approaches for clock gating
have been proposed. Two prominent techniques are precomputation [ 11 ]and guarded evaluation
[ 218 ].

Introduced by Alidina, Monteiro, Devadas, Ghosh, and Papefthymiou, precomputation,
as the name suggests, aims to derive a precomputation circuit for a logic block. The precom-
putation circuit under some condition subsumes the operation of the larger logic block. One
example would be a multiplexed precomputation architecture in which a large logic block F is
split into two new separate blocks F ( x 1), where x is a control variable that also

drives the output multiplexor for these two blocks. Only the block producing the output needs
to be evaluated, while the operation of the other block can be gated by x .
In contrast, guarded evaluation , proposed by Tiwari, Malik, and Ashar, aims to shut
down—clock gate— part of the original circuit which, under some condition, is not needed in
evaluating the final output. The idea (shown in Figure 4.3) is to find a subset F of the gates of
the original circuit that generate a signal x . If there is a readily available signal S that determines
whether the evaluation of the signal x has any effect on the final output of the whole circuit,
then S can be used to clock gate F . In other words, S determines whether x is a don't care for the
final output. If x is a don't care, F need not switch for the correct evaluation of the output. Even
if S is not available at the start of the computation, it can still be used to advantage in stopping
the evaluation of F . However, in such a case, partial evaluation of F takes away some of the
power savings. Tiwari et al. develop a theoretical framework and the related algorithms for
automatically determining parts of a circuit that can be disabled on a per-cycle basis. Applying
their methodology on a number of benchmark circuits, the authors show substantial power
savings.

= 0) and F ( x =