Using Voltage and Frequency Adjustments toManage Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 40

FIGURE 3.7: Work steering for a fast and a slow pipeline. Reproduced from [ 76 ]. Copyright 2002
IEEE.
and-observe approach. An instruction is delayed for a number of cycles and then observed to
see if it becomes critical.
Criticality, in turn, is tested with a token that is passed from instruction to instruction,
starting from the delayed instruction, and passed to all dependent instructions. The token
is dropped if it is not passed to an instruction at the very last moment before it becomes
ready to execute. In other words, the token is dropped if it has slack. If the token is still in
existence well after an instruction is delayed, then the instruction, thus far, is in the critical
path.
Slack determined by sampling is stored, per-instruction, in a PC-indexed predictor.
This prediction is used in subsequent dynamic instances of the instruction for steering. If an
instruction's predicted slack can accommodate the increased latency of a slow pipeline, then the
instruction can be steered to this pipeline for execution without an impact on the performance.
Fields et al. confirm this in their results, showing that a control policy based on slack prediction
is second-best, in terms of performance, only to the ideal case of having two fast pipelines
instead of a fast and a slow pipeline [ 76 ]. However, execution in the slow pipeline yields
significant benefits in power consumption.
3.4.3 DVFS for Multi-Core Processors
As chip multiprocessors (CMPs) become the predominant general-purpose, high-performance
microprocessor platform, it becomes important to consider how DVFS management can be
applied to them most effectively. One major design decision concerns whether to apply DVFS
at the chip level or at the per-core level. As with other MCD designs, per-core DVFS is
considered more expensive; it requires more than one power/clock domain per chip, and
synchronizer circuits are required to avoid metastability between domains. On the other hand,
multiple clock domains may be employed anyway for circuit design or reliability reasons, in
addition to voltage and frequency control.