Using Voltage and Frequency Adjustments toManage Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 32

FIGURE 3.2: Dynamic compilation system. Reproduced from [ 226 ]. Copyright 2005 IEEE.
3.3.2 Online Dynamic Compiler analysis
While offline compiler analysis can use global program knowledge and detailed analysis to plan
DVFS adjustments, it lacks knowledge about runtime characteristics such as data inputs and
caching behavior that can greatly impact program behavior. Thus, much work has been done
on more dynamic techniques for determining where to place DVFS adjustments.
In a more recent work by Wu et al. the authors studied methods using dynamic compila-
tion techniques to analyze program behavior and also to dynamically insert DVFS adjustments
at the locations determined to be most fruitful [ 226 ]. Wu et al. implemented a prototype of this
runtime DVFS optimizer (RDO) and integrated it into an industrial-strength dynamic opti-
mization system (a variant of the Intel PIN system [ 159 ]). A block diagram of their approach
is shown in Figure 3.2.
The dynamic optimizer begins by dispatching “cold” code for execution. A monitor
determines whether this code is frequently executed. In this case, the RDO optimization is
applied along with other conventional performance optimizations of the dynamic optimizer.
The RDO flowchart is depicted in Figure 3.3. The first order of business is to determine
the “hotness” of functions and first-level loops in main(). These code regions are instrumented
for frequency-of-execution profiling. If they become “hot,” they are then considered for DVFS
optimization. To decide on the optimization, an analytic model determines whether a region is
memory-bound or CPU-bound. If the region is clearly memory-bound, it is instrumented with
DVFS mode-set instructions. This is because memory-bound code has enough slack so that