Using Voltage and Frequency Adjustments toManage Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 26

research arena, but we urge readers to explore research ideas from the design automation and
other communities as well.
3.2 SYSTEM-LEVEL DVFS
3.2.1 Eliminating Idle Time
Architectural techniques for dynamic voltage and frequency scaling first appeared in the lit-
erature pertaining to the system (or operating system) level. Commercial implementations
controlled at this level are also the most common form of DVFS (e.g., Intel's Enhanced
SpeedStep and AMD's PowerNow! TM ).
Wiser, Welchm, Demers, and Shenker, all of Xerox PARC, first published on this type
of DVFS [ 223 ]. Wiser et al. observed that idle time represents energy waste . To understand
why this is, consider the case of a processor finishing up all its tasks well within the time of a
scheduling quantum. The remaining time until the end of the quantum is idle time . Typically,
an idle loop is running in this time but let us assume that the processor can be stopped and
enter a sleep mode during this time. One could surmise that a profitable policy would be to go
as fast as possible, finish up all the work and then enter the sleep mode for the idle time and
expend little or no energy. But that is not so.
As an example, let us assume that the time needed to finish up all the work is half the
time quantum. The idle time would then be the other half. At best, if the sleep mode wastes
no energy, half the energy that would be expended in a busy quantum can be saved in this
way. Consider now the case where we have the ability to dynamically scale both frequency and
voltage. Just by slowing down the clock, the work that needs to be done can be stretched to
cover the entire quantum. In our example, assuming that the clock period is doubled (frequency
is halved) to eliminate the idle time, power consumption drops by half. Thus, the energy needed
to complete the work is the same as going full speed for half the quantum and idling for
the rest. But, on top of that we can also scale the voltage which reduces power consumption
quadratically. The end result, with DVFS, is that the more we stretch a fixed amount of work
themorewegain,thusturningidletimeinto opportunity cost . 1
With this motivation, Wiser et al. propose three scheduling algorithms, called OPT,
FUTURE, and PAST, aiming to eliminate idle time. Their work specifically targets idle time
as it is experienced in the operating system, i.e., the time taken by the idle loop, or I/O waiting
time. Of course, when one considers very long idle periods (e.g., periods measured in seconds)
and includes components such as the display or the disk of a portable system in the accounting
for total power, the best policy is to shut down all components (since the display and disk surpass
1 An important point here is that static power consumption is not taken into account in this reasoning. We will
return to this in Chapter 5 where we discuss the implications of static power in relation to DVFS.