Using Voltage and Frequency Adjustments toManage Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 24

scaling improves EDP (because the reduction in power outpaces the reduction in performance),
it can do no better than break even on the ED 2 P metric (and this, only when the scaling factors
for frequency and voltage are the same).
Nonetheless, DVFS is appealing first because max-power limits may welcome max-power
reductions even if the energy is not reduced much. In addition, DVFS is appealing because
often we can discern ways, as this chapter will discuss, to reduce clock frequency without having
the workload experience a proportional reduction in performance.
3.1.1 Design Issues and Overview
From an architect's perspective, key design issues for DVFS include the following:
(1) At what level should the DVFS control policies operate? Fundamentally, DVFS ap-
proaches exploit slack . Slack can appear at different levels and various DVFS approaches have
been proposed for each level. Approaches operating at the same level share a similar set of
mechanisms, constraints, and available information. We can discern three major levels where
DVFS decisions can be made:
System-level based on system slack : At this level, the idleness of the whole system is the
factor that drives DVFS decisions (Section 3.2). In many cases, decisions are taken
according to system load. The whole processor (or embedded system, wireless system,
etc.) is typically voltage/frequency scaled to eliminate idle periods.
Program- or program-phase-level based on instruction slack : Here, decisions are taken
according to program (or program phase) behavior (Section 3.3 for a single clock do-
main and Section 3.4 for multiple clock domains). Instruction Slack due to long-latency
memory operations is typically exploited at this level for DVFS in single-threaded pro-
grams. In multi-core processors, the ability to run parallel (multi-threaded) programs
opens up the possibility for the parallel program behavior to drive voltage/frequency
decisions.
Hardware-level based on hardware slack : Finally, a recent approach, called Razor, goes
below the program level, right to the hardware (Section 3.5). Razor tries to exploit slack
hidden in hardware operation. This slack exists because of margins needed to isolate
each hardware abstraction layer from variations in lower levels. This slack is exploited
similarly to the way idle time is exploited at the system level.
(2) How will the DVFS settings be selected and orchestrated? In some cases, DVFS ap-
proaches may allow software to adjust a register which encodes the desired ( V , f ) setting. In
other cases, the choices will be made dynamically “under the covers” by hardware mechanisms