Modeling, Simulation, and Measurement - Computer Architecture Techniques for Power-Efficiency - page 18

their behavior would include power estimates first. Subsequent versions of Cacti have refined
the dynamic power models and included leakage power models as well [ 217 ].
Whole-processor power simulators : While local power models for individual processor struc-
tures are a useful first step, processor design still required that architects be able to make high-
level, whole-processor analyses of power trade-offs, and to do so early enough in the design
pipeline that useful adjustments could be chosen. Thus, in 2000, two whole-processor power
simulation tools were discussed. SimplePower was introduced as a means of doing detailed
“whole processor” analyses of dynamic power. It focused on in-order five-stage pipelines, with
detailed models of integer ALU power as well as other regions of the chip.
Also introduced in 2000, the Wattch tool, like SimplePower, sought to provide detailed
whole-processor data on dynamic power [ 38 ]. Because it was built as an additional software
module to be used with the widely used SimpleScalar tool [ 40 ], Wattch has seen wide use
among architects. Wattch draws its cache modeling from Cacti, while providing parameterized
activity-based estimates for other units as well. Wattch simulates an out-of-order super-scalar
pipeline.
Both SimplePower and Wattch are examples of simulators based on analytic power
modeling techniques. In contrast, the IBM PowerTimer tool represents a microprocessor
power simulator based on empirical techniques [ 36 ]. Namely, PowerTimer estimates the power
consumption of a particular architectural module by using the measured power consumption of
the corresponding module in an existing reference microprocessor, and scaling it appropriate
to the size and design changes. For example, if the modeled design is identical to the reference
design except for a larger first-level cache, then all of its per-module power estimates would be
drawn from the reference chip's measurements. For accesses to the first-level cache, the power
to be “charged” would be calculated by the reference chip's cache power scaled by the expected
power scaling factor. This scaling factor would most simply be based on capacitance changes,
but might also include other more sophisticated effects based on cache design and layout.
Empirical power models tend to be most used in industry settings, because these architects
are able to access detailed power measurements from previous reference designs. While they
are quite useful for power projections into future variants of a design, they are more difficult for
larger design changes where the per-module proportional scaling cannot easily be applied.
2.4 MEASUREMENT
While simulation is appealing for early-stage design evaluations, it is difficult or impossible for
simulators to be deeply detailed and have sufficient speed for thorough parameter explorations.
Thus, for some studies, it becomes appealing to measure power/thermal metrics directly, rather
than simulating them.