Modeling, Simulation, and Measurement - Computer Architecture Techniques for Power-Efficiency - page 17

material characteristics that influence heat conductivity, and another constant c represents the
material's heat capacity:

R = t / kA ,

C = ctA .

Such R and C values are computed both based on the areas (A) of different microar-
chitectural units, as well as on the areas, thickness (t), and materials of heat sinks and heat
spreaders. Thus, these RC networks can be composed automatically from parameters that give
the area and makeup of the microarchitecture and supporting heatsinks.
Once the RC network has been formed, it is translated into a set of differential equations,
and is solved numerically using a fourth-order Runge-Kutta method. Because temperature
varies slowly relative to processor speeds, the numerical solver need not be invoked on every
simulated cycle. Instead, typical approaches involve a solver roughly every 10 000 processor
cycles in order to track thermal trends on timescales of tens to hundreds of microseconds.

2.3 POWER SIMULATION
While the circuit design and design automation research communities researched CMOS
power issues earlier, architects first began studying power issues for CMOS designs in earnest
in the early to mid 1990s [ 88 ]. At first, architecture researchers interested in studying power
optimizations reported their quantitative results in terms of “proxy” metrics. For example,
Grunwald et al. studied power savings garnered by using confidence estimation to limit branch
speculation in cases where the branch was not very likely to succeed [ 88 ]. In this work, they
reported their power savings in terms of how many fewer mis-speculated instructions were
executed when confidence estimators are used.
While metrics like “mis-speculation reduction” can be useful and intuitive proxies for
reporting some results, their drawback is that they do not offer a common currency by
which to compare the power benefits of multiple distinct power-saving opportunities. Fur-
thermore, they do not extend naturally to studies of thermal issues and other power-related
problems.
For these reasons, architects in the late 1990s began working on architecture-level power
models that aim to directly estimate power and energy, just as cycle-level architecture simulators
aim to directly estimate performance.
Memory system simulation : An early example of power simulation came from the Cacti
tool. The Cacti tool was developed to study memory hierarchies in detail. While Cacti 1.0
[ 224 ] primarily provided estimates of area and latency for parameterized cache designs, Cacti
2.0 added in a dynamic power model. Because caches are almost always built as very regular array
structures of SRAM cells with supporting circuitry, it is natural that parameterized models for