Modeling, Simulation, and Measurement - Computer Architecture Techniques for Power-Efficiency - page 12

2.2.1 Dynamic-power Models
The most widely used and well-understood power models among architects are those that focus
on dynamic power consumption. Because dynamic power greatly exceeded leakage power until
recently, it is reasonable that early architects focused their attention on how to measure and
model its effects.
Drawing from the familiar CV 2 Af equation previously presented, dynamic power models
typically focus on characterizing these terms. We start by considering a scenario in which V and
f are viewed as fixed, focusing mainly on C and A . We then move to consider other approaches
in which power predictions across technology generations (and therefore spanning values of V
and f ) are attempted.
At a high level, dynamic-power models can be divided into analytical and empirical
techniques. Analytical techniques seek to express power behavior in terms of equations pa-
rameterized by module size or other characteristics. Empirical techniques, in contrast, have
focused on predicting the behavior of one possible chip design by appropriately scaling per-
module power behaviors observed for some other measured chip design. We focus on analytic
models here, but discuss empirical approaches when we touch on dynamic power simulation in
Section 2.3.
Early work in the architecture-level power modeling mainly focused on caches [ 20 , 119 ,
123 , 213 ]. This was in part due to the fact that caches represented up to 40% of the power budget
for some low-power embedded microprocessors [ 169 ]. In addition, caches are regular structures
which are easier to model. Both C and A can be fairly readily expressed using parameterizations
of cache size and organization. Thus, it makes sense that attention would be focused here
earlier.
Both capacitance and activity factor are expressions where the architect has some high-
level understanding and control, even though the ultimate details are dependent on the partic-
ulars of the circuit design chosen.
The activity factor is related both to the application program being executed (both its
data patterns and control) and to some circuit design choices. For example, for circuits that
pre-charge and discharge on every cycle (i.e., double-ended array bitlines) an A of 1 is used.
For wires that represent data buses, the activity factor can be chosen based on knowledge of
the 1/0 statistics in the data set being studied. In addition, clock gating (techniques that “gate”
the clock control signal to prevent its toggling within a particular sub-unit) reduce a sub-unit's
activity factor during idle periods.
Estimating Capacitance : Like activity factor, capacitance depends in part on circuit design
choices. Even in relatively regular array structures, the aspect ratio, number of wire routing
layers, or other layout choices can influence capacitance. Nonetheless, with modest amounts
of knowledge about circuit design style, usefully accurate architecture-level power models are