Introduction - Computer Architecture Techniques for Power-Efficiency - page 7

The structure of the topic is as follows. Chapter 2 offers deeper background information
on power dissipation and describes the primary strategies for modeling, simulating, and mea-
suring power and related metrics. The rationale for this chapter is that one cannot optimize
power for a particular system if one lacks a clear view of that system's power behavior. Therefore,
we view Chapter 2 as offering resources on experimental and measurement infrastructure that
every architect can tailor to the needs of their research or design.
Chapters 3 and 4 cover aspects of reducing dynamic power in CMOS computer systems.
We have chosen to arrange this material in terms of the basic equation for CMOS dynamic
power consumption: CV 2 Af . Thus, Chapter 3 covers strategies for managing power via voltage
( V ) and clock frequency ( f ). This includes both dynamic voltage and frequency scaling, as well
as other possibilities.
Chapter 4 focuses on the activity factor ( A ) and capacitance ( C ). Activity factor is so
intrinsically tied to how architectural units are organized and used that it represents much
of the most straightforward power optimizations available to a computer architect. Other
important methods of reducing power consumption manage the capacitance ( C ) factor in
designs. At the most qualitative but intuitive level, shorter wires have lower capacitance; thus,
microarchitectures with simple local structures are likely to result in improved dynamic power
behavior. Such insights have driven many power-aware designs, such as memory banking
optimizations and even the overwhelming current trend towards chip multiprocessors (CMPs).
We have grouped the discussion of “ A ”and“ C ” together because they are often linked in design
strategies. For example, one can reduce the activity factor on buses or in arithmetic units by
segmenting long wires into individually controllable modules; this affects both C and A .
While dynamic power is important and represents much of the prior work in power-
aware architecture, there is no avoiding the fact that leakage energy has emerged as an equal or
greater challenge for computer architects today. Thus, in Chapter 5 we present a discussion of
techniques for lower static or leakage power in current and future computer systems. Finally,
Chapter 6 offers our conclusions.