Conclusions - Computer Architecture Techniques for Power-Efficiency - page 184

packet-switched) network-on-chip (NoC). Interesting future research directions must focus
on power-efficient implementations of these interconnects, as well as optimization of the
inter-processor communication patterns in order to save power and energy.
6.3 LEAKAGE POWER REDUCTIONS: STATUS
AND FUTURE TRENDS
Leakage energy remains the most vexing of the problems raised in this topic. Below the
architecture level, process technology has come up with solutions to reduce gate leakage (e.g.,
high- k dielectrics) but subthreshold leakage remains a problem. Circuit techniques to “power-
gate” regions of a design are promising, but continue to require increases in wiring or in cicuit
complexity. Furthermore, in contrast to dynamic power, there have been fewer good abstractions
for how architects can reason about leakage energy and control it, without dropping to circuit-
level design.
Currently and into the future, the leakage problem is exacerbated by high-performance
chips operating at or near the top of their thermal envelope. Significant effort must be expended
at the architectural level to fight leakage even at the smallest structures to avoid thermal runaway
effects because of the exponential relation of subthreshold leakage to temperature. Scaling the
supply voltage does reduce both the dynamic power and leakage power (e.g., drowsy techniques)
but, as we mentioned above, reduced supply voltages significantly compromise reliability of the
upcoming nanoscale technologies. Thus, drowsy techniques are expected to cause significant
increases in soft errors.
Overall, we see leakage management as one of the key areas of future architecture-level
power research. A particularly pressing need is on general techniques and abstractions for
reasoning about leakage in more circuit-oblivious ways.
6.4 FINAL SUMMARY
The past decade has seen a dramatic evolution in how architects view power dissipation and
related issues. Roughly ten years ago when architecture conferences began publishing power-
oriented papers, they were somewhat at the fringe of the community, with most attention still
be focused on performance-enhancing/power-oblivious techniques. This was followed by years
in which the “power problem” saw intense research interest and a flurry of interesting and
varied results on how to build power-efficiency into a range of microprocessor architectures and
structures.
We now appear to be at a new inflection point in the timeline of architectural power
research. In particular, power now plays some role in almost every paper or technique proposed,