Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 179

FIGURE 5.23: Symmetric versus asymmetric SRAM cell. Voltage levels (shaded 1 and 0) and leakage
paths are shown in the ordinary symmetric cell when it is holding a “0.” The Asymmetric Cell utilizes
high- V T (low-leakage but slow) transistors for N2, P1, and N4 (the leakage paths). The result is low
leakage in state 0 (reduced by 40 ◦ ) but also higher latencies in discharging the bitlines (46% for the BL
and 12% for the BLB). Reproduced from [ 18 ]. Copyright 2003 IEEE.

far outstrips the number of ones in memory. And this holds for both data and instructions,
regardless of whether they are actively or rarely accessed.
This observation implies that the number of zero bits in the cache is also proportionally
greater than the number of ones. We have encountered a similar approach for dynamic power
in Chapter 4, Section 4.4.1, but at the byte level. Villa, Zhang, and Asanovic observe that a
large percentage of bytes in the memory system are zero, and therefore can be represented by
a single bit, the Zero Indicator Bit (ZIB) [ 221 ]. Although they operate different granularity
and for different kinds of power (dynamic versus leakage), the Azizi et al. and the Villa et al.
techniques are closely related.
The idea in the Azizi et al. technique is to selectively use high- V T devices to build a
memory cell that is more power-efficient in holding zeros than ones. Such a cell is shown in
Figure 5.23 (on the right) and contrasted to a standard cell (on the left). The transistors on
the leakage paths (when the standard cell holds a zero) are replaced with high- V T devices.
The resulting asymmetry saves 40 of leakage when holding a zero—holding a one makes no

difference. At the same time, an asymmetry is created in the access times: the discharge of the
bit-line (BL) is slowed down by 46%, whereas the discharge of the negated bit-line (BLB) is
slowed much less, only 12%. In contrast, building a whole cell out of high- V T transistors saves
leakage no matter what the stored value but the access speed is symmetrically impaired in both
bitlines (BL and BLB).
The asymmetry in the access times proves to be the key in making the scheme perform
on a par with ordinary cells. With a novel sense-amp design, complete with dummy bitlines

×