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FIGURE 5.22: Gradual sleep mode. Reproduced from [ 69 ]. Copyright 2002 IEEE.
with power gating, the question then becomes, whether the idle time of the functional units is
long enough for the gains in leakage energy to outpace the penalty of entering the low-leakage
mode. Typically, it may not be profitable to enter in low-leakage mode for very short idle
periods.
Unfortunately, the distribution of the idle periods for the integer functional units is
dominated by short times [ 69 ]. This means that an overly aggressive policy to enter the sleep
mode is probably not optimal. For this reason, Dropsho et al. propose a gradual sleep policy
that puts the functional unit in sleep mode in stages. The technique is shown in Figure 5.22.
The functional unit is divided in slices which are put in sleep mode consecutively as long as the
functional unit remains idle. As soon as it is needed again, all slices are brought back to active
mode and are precharged.
The gradual sleep technique can tie very well with the narrow-width operand techniques
discussed in Chapter 4, Section 4.3, in relation to dynamic power. However, such a possibility
was not considered. Nevertheless, the gradual sleep technique effectively harvests the idle times
of the functional units for leakage savings without incurring large penalties, thus, making it
very difficult for a more sophisticated technique to do much better.
5.4.4 Asymmetric Memory Cells
Using dual- V T in functional units relies on timing asymmetries in the circuits. Non-critical paths
can be populated by slower, high- V T transistors taking up some of the time slack. Memory
structures, however, are regular when it comes to timing. Azizi, Moshovos, and Najm, exploit
a different kind of asymmetry, a storage asymmetry , to selectively introduce high V T devices in
SRAM design [ 17 , 18 ].
Their technique relies on an imbalance in the number of ones and zeros that appears
in the memory system for ordinary programs. The observation is that the number of zeros by
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