Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 176

low-leakage) everywhere else; as long as the increased delay of the high- V T devices can
be hidden in the slack this saves leakage without affecting speed. An example of this
technique is in dynamic domino logic [ 124 ] which is described in detail in Section 5.4.3.
The asymmetric cell design presented in Section 5.4.4 is an analogous methodology
but is intended for memory and exploits a different storage asymmetry [ 17 , 18 ].
The second design methodology uses high-V T sleep transistors to gate off the power
to high-speed, low- V T , logic when such a logic is idle. This is similar to the gated- V dd
approach mentioned above, the difference being the use of dual threshold voltages. The
leakage reduction in the low- V T logic is still a result of the stacking effect as described
previously, but now enhanced by the presence of the high-V T sleep transistors. We will
not expand separately on this methodology since it is a dual- V T version of the gated- V dd
approach already described in Section 5.2.
5.4.3 Dual- V T in Functional Units
One of the few architectural-level studies for the use of dual- V T in functional units is by Drop-
sho, Kursun, Albonesi, Dwarkadas, and Friedman [ 69 ]. For performance reasons, functional
units are typically designed using dynamic domino logic instead of static CMOS. Figure 5.20
contrasts an AND gate in static CMOS and in dynamic domino logic. In terms of dynamic
power the difference in the two designs is that, every clock cycle, the domino logic is charged
and discharged (if needed) by the evaluation of its inputs. As mentioned in Chapter 4, Section
4.2, this can consume power even when the inputs do not change . The only way out is to stop
the clock, i.e., clock gate the entire circuit not just its inputs. With respect to static power,
FIGURE 5.20: AND gate in static CMOS and in dynamic domino logic. The “Dynamic” node in (b)
is precharged during the low phase of the clock. Inputs are evaluated during the high phase of the clock
and can discharge the dynamic node. Reproduced from [ 69 ]. Copyright 2002 IEEE.