Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 169

Soft errors occur when a particle strike at a circuit node generates enough charge to
cause a bit flip at that node. This happens when the collected charge from the strike exceeds
a quantity known as Q critical , which is proportional to the node capacitance and the supply
voltage. The Soft Error Rate ( SER ) is exponentially dependent on Q critical and proportional to
the cross-section area of the node (CS) and the environmental radiation flux ( N flux ):

e − Q critical SER = N flux / × CS × .

Q s

The exponential dependence to Q critical translates to an exponential dependence on the
supply voltage. This means that DVS techniques such as the drowsy technique have a dramatic
effect on reliability—increasing by at least an order of magnitude the SER. In contrast, cache
decay improves reliability but invalidating a significant portion of the data, thus, reducing their
exposure to soft errors. In addition, the early writeback induced by decay, helps protect dirty
data by writing them back to the memory system.
Degalahal et al. further exploit decay's early writeback property in an adaptive error-
protection scheme. The idea is to protect differently clean and dirty data, assuming that
an error on clean data can be corrected by re-fetching the data from a lower level of the
hierarchy. This leads to 11% savings in the dynamic energy expended on error protection in
the L1.
A related technique to enhance reliability was proposed by Zhang, Gurumurthi, Kan-
demir, and Sivasubramaniam [ 245 ]. The technique, called In-Cache Replication ( ICR ), is based
on cache decay and replicates live cache lines in the dead space of the cache. Space vacated by
dead lines is reclaimed and used to hold replicas of live lines. Replication can be performed
vertically, across sets, by making a copy at a fixed distance from the original's set, or within the
same set by reclaiming empty associative ways. Zhang et al. examine a number of variations
of this idea and show that reliability can be significantly enhanced without compromising the
performance [ 245 ].

5.3.6 Compiler Approaches for Decay and Drowsy Mode
All approaches to control leakage in caches, thus far, are based on hardware monitoring (e.g.,
decay) or even simple hardware techniques (e.g., the Simple policy for the drowsy mode).
Compilers, however, can play an important role with the help of leakage control instructions.
Compiler involvement, assisted by profiling, has been initially proposed along with the
hardware implementation of cache decay [ 127 ]. The compiler approach assumes the availability
of instructions that access cache lines and turn them off immediately after. The idea is to find
what instructions are last-use instructions for cache lines and replace them with leakage-control
instructions. Unfortunately, it is difficult for the compiler to do a thorough analysis of the data
without the help of run-time information. Profiling is necessary for this approach to work but