Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 159

mispredictions all point to idleness of the functional units until the processor pipelines recover
and return to full operation.
Hu et al. concentrate on branch mispredictions. Upon detecting a mispredict, the func-
tional units are put immediately into sleep mode without waiting for the normal decay interval.
This simple rule extends the powered-down time of the functional units without incurring any
additional performance penalty. The use of clues increases the percentage of cycles in sleep
mode for a given performance loss, or, conversely, for the same percentage of cycles in sleep
mode the use of clues eases the performance impact. Similarly to branch mispredictions, other
events can also provide useful hints for the idleness of the functional units but have not been
studied further.
5.3 ARCHITECTURAL TECHNIQUES USING
THE DROWSY EFFECT
One disadvantage of the gated V dd mechanism is that it destroys state. The first approaches to
control leakage based on this mechanism (DRI cache, cache decay, AMC, etc.) are known as
non-state-preserving. In the case of cache decay and related approaches, the reasoning is that
most of the lost state is useless anyway. And that would be fine if it were not for the problem
of mistakes—decay-induced misses—which actually harm performance. The drowsy effect was
proposed to address this problem, introducing a new class of state-preserving leakage-reduction
techniques.
5.3.1 Drowsy Data Caches
In response to the gated- V dd problem of losing state, Flautner, Kim, Martin, Blaauw, and
Mudge proposed another approach to curb leakage in memory cells [ 77 ]. The drowsy mode
is a low supply voltage mode for the memory cells, i.e., Dynamic Voltage Scaling (DVS) for
leakage.
Similar to the DVS approaches discussed in Chapter 2, this type of DVS also has to do
with idleness; but not with frequency scaling. Memory cells which are idle, i.e., are not actively
accessed, can be voltage-scaled into a drowsy mode. In this mode, transistors leak much less
than with a full V dd as explained in Section 5.1.1. Figure 5.13 shows the design of a drowsy
cache from [ 77 ]. A “drowsy” bit controls the two levels of supply voltage ( V dd or V ddLow )tothe
memory cells of a cache line. Memory cells are in drowsy mode when fed from V ddLow .
The leakage reduction of the drowsy mode is not as profound as that of the gated- V dd
approach which completely cuts off the path to V dd (or, equivalently, to ground). However,
allowing for some nonzero supply voltage preserves the state of the memory cell. This happens
as long as the supply voltage is strong enough to replenish the charge in the cell's internal nodes.
However, a memory cell in drowsy mode cannot be accessed with the full- V dd circuitry of the