Introduction - Computer Architecture Techniques for Power-Efficiency - page 4

as dynamic voltage and frequency scaling (DVFS) recognize periods when lower microprocessor
performance is acceptable (e.g., in memory-bound or latency-tolerant regions of code) and
reduce ( V , f ) accordingly.

1.2.2 Leakage
While dynamic power dissipation represented the predominant factor in CMOS power con-
sumption for many years, leakage energy has been increasingly prominent in recent technologies.
Representing roughly 20% or more of power dissipation in current designs, its proportion is
expected to increase in the future [ 32 , 113 ]. Leakage energy can come from several sources,
including gate leakage and sub-threshold leakage. Gate leakage is increasing in importance
and will be discussed in Chapter 5. Here, we briefly introduce only the concepts behind sub-
threshold leakage because they are fundamental to this chapter's trends discussion.
Sub-threshold leakage power represents the power dissipated by a transistor whose gate
is intended to be off. While our idealized view of transistors is that they operate as switches, the
reality is that the relationship between current and voltage (the so-called IV curve depicted in
Figure 1.2) is analog and shows a non-zero amount of current even for voltages lower than the
threshold voltage ( V th ) at which the transistor is viewed as switching “on.” This modest current
for V dd less than V th is referred to as the sub-threshold current. The power dissipation resulting
from this current is referred to as the sub-threshold leakage power, because the transistor
appears to leak charge to ground. Sub-threshold leakage power is given by the following
simplified equation:

V k e − qV th / ( ak a T ) P = .

FIGURE 1.2: Example of an “ IV ” curve for a semiconductor diode. Although we informally treat
semiconductors as switches, their non-ideal analog behavior leads to leakage currents and other effects.