Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 156

in a 6T cell will be maintained as long as that cell is connected to the source and drain voltages
( V dd and ground).
But leakage-control techniques, such as those discussed in Section 5.3, carry an overhead
(per entry) that cannot be easily amortized in smaller structures or structures with very small
entries. Instead, Hu et al. entertain the idea of using quasi-static, self-decaying , four-transistor
(4T) memory cells, especially for branch predictors and branch target buffers (BTBs) [ 106 ].
The reasoning behind this approach is that quasi-static 4T cells ( Figure 5.12, right side)—
which have no connection to V dd —provide decay functionality inherently: if not accessed, their
charge gradually leaks away at a rate that is a function of the cell's specific design and operating
temperature. Conversely, they are recharged upon access. 4T cells are, therefore, uniquely well-
suited for decaying structures, such as branch predictors and BTBs, where the overhead of a
6T-cell decay technique would be prohibitive.
BTB and predictor structures —This behavior is conducive for decay, since the data held is
both transient and predictive. It is transient in the sense that data which has not been used for
a sufficiently long time has decayed. It is predictive in the sense that allowing a value to leak
away even if it will be used again does not harm correctness. Using a decayed value may mereley
cause a misprediction that can be handled by existing hardware. This is a key difference from
caches, where using decayed data leads to incorrect execution of the program.
The key design points for implementing decay in branch predictors and BTB's are the
decay interval—which can be affected by circuit design—and the granularity of access—how
many entries are accessed simultaneously because of the layout of the branch predictor or BTB
structure. Their combination determines the active ratio and thus, the leakage savings and the
resultant performance [ 106 ].
4T decay is met with some skepticism because it is an analog design with many factors
that could affect it. Many issues, including metastability issues, dependence on temperature,
etc., need to be addressed to deploy such a technique in practice. It does hold the promise,
however, for very low leakage since only the memory cells that are actively used can dissipate
leakage power.
5.2.6 Gated V dd Approaches for Functional Units
The first leakage-control policies, using gated V dd (e.g., DRI, cache decay, AMC), target
caches. In this context, the main energy trade-off is between the saved leakage energy and the
extra dynamic power consumed by misses on the turned-off cache lines. The extra energy cost
of switching the sleep transistor on and off was not of immediate concern. This, however, was
of little consequence, since the timescales for inactivity (and therefore the potential leakage
savings) are such that they could easily absorb the sleep transistor switching cost without
difficulty. In other words, the cost of switching the sleep transistor and recharging the internal