Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 155

L1 generation L1 generation

live (dirty)

dead time

L1 timeline

eviction

1st write

L2 timeline

Conservative

{

Periods L2 line
is turned-off

Speculative-IV

Speculative-II (non-dirty line)

L2 decay-induced miss

FIGURE 5.11: Time diagrams for the non-inclusion policies. Adapted from [ 154 ].

Not surprisingly, simulations show that the conservative policy does not save as much
leakage as the others but, on the other hand, does not hurt performance either. Speculative-II
saves the most energy by being very aggressive, but degrades performance significantly hurting
the resulting EDP. Although Speculative-IV saves less leakage due to early reactivation, it also
avoids going to the main memory as extensively as Speculative-II does. Thus, it consumes less
dynamic energy, performs better and yields a better EDP than Speculative-II. It is also possible
to combine cache decay in the L1 with an L2 policy (especially if it is state preserving) for
significantly better results than just having cache decay at both levels [ 154 ].

5.2.5 Four-Transistor Memory Cell Decay
Decay in static RAM mimics the fleeting nature of dynamic RAM: data that are not touched or
refreshed, are lost. The idea of using four-transistor quasi-static cells for decay stems from this
parallel. Hu et al. make the observation that much of on-chip storage is devoted to transient,
often very short-lived, data. Despite this, virtually all chip designs use array structures based on
six-transistor SRAM cells that store data indefinitely ( Figure 5.12, left side). A charge stored

FIGURE 5.12: 6T versus 4T memory cell. Adapted from [ 106 ].