Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 149

FIGURE 5.8: Adaptive per-cache-line decay. The decay interval is counted by the 2-bit local
counter and the line is decayed when the counter reaches state 10 (note the Gray coding for
switching efficiency). After the line is decayed the counter starts counting again but this time to
gauge the arrival time of the next access. In this particular example, if the next access comes when the
counter is in its first state (00) the (unknown) access is taken to be a decayed-induced miss and the
decay interval is doubled; the decay interval does not change in the middle two states of the counter,
while if the next access comes when the counter has saturated at state 10, the access is taken to be a
replacement and the decay interval is halved. Reproduced from [ 127 ]. Copyright 2001 IEEE.
is doubled in this case. In contrast, an access that comes much later (after the local counter
advances a few more steps) is taken to be an access to a different cache line—a replacement.
In [ 127 ] if the miss occurs with the local counter stuck at its highest value, the decay interval
is to be too large and is halved to reduce the fixed overhead; otherwise, it is left unchanged.
Global decay interval adaptive techniques : The concept of cache decay was independently
invented by Zhou, Toburen, Rotenberg, and Conte, who proposed an adaptive policy to
dynamically adjust the global (for the entire cache) decay interval [ 250 ]. Their adaptive scheme
is called Adaptive Mode Control (AMC). Its adaptation is based on a performance feedback
loop: the decay interval is adjusted so that the number of decay-induced misses—i.e., the
performance loss—is bounded. In contrast to the per-cache-line adaptive decay which can
only be controlled indirectly, this technique allows excellent control over the trade-off between
performance and leakage-reduction.
The underlying mechanism to turn off dead cache lines is similar to cache decay (see
Figure 5.9). 10 A two-tier hierarchy of counters, consisting of local counters per cache line (called
Line Idle Counters ,or LICs ) and a global counter (called LIC update interval counter ) measure the
decay interval. In contrast to cache decay, the global counter (the LIC update interval counter)
remains fixed. The global LIC update interval is set to a value of 2048 cycles that is not too long
to hamper decay, neither not too short to force frequent switching upon the local LICs. As
each LIC advances, it is compared to a threshold. If the LIC exceeds the threshold the line is
decayed. 11 The comparisons take place in each cache line using a local comparator called Mode
10 AMC also uses a gated- V dd mechanism to turn off cache lines which makes it a non-state-preserving technique
but—like cache decay—this is a choice , not an inherent property of the technique.
11 Recall that in cache decay the local counters do not compare against anything but simply decay the cache line
when they reach their “last” (saturation) state.