Introduction - Computer Architecture Techniques for Power-Efficiency - page 3

1.2 CMOS POWER CONSUMPTION: A QUICK PRIMER
The remainder of this topic focuses primarily on the issues facing computer architects in
managing and optimizing CMOS power dissipation. We offer a brief primer here on these
issues, with more detail given in Chapter 2.
CMOS power consumption can be divided into several categories: dynamic power,
leakage power, glitching power, and others. We discuss these in the subsections that follow.

1.2.1 Dynamic Power
The dominant power category for many years has been dynamic power, which is given by the
proportionality: P (proportional to) CV 2 Af . Here, C is the load capacitance, V is the supply

voltage, A is the activity factor and f is the operating frequency. Each of these is described in
greater detail below.
Capacitance ( C ): To first order (i.e., the architect's point of view rather than the more de-
tailed view of a circuit designer), aggregate load capacitance largely depends on the wire lengths
of on-chip structures. Architects can influence this metric in several ways. As one example,
building four smaller processor cores on-chip, rather than one large monolithic processor, is
likely to reduce average wire lengths considerably, since most wires will interconnect units
within a single core. Likewise, smaller cache memories or independent banks of cache can also
reduce wire lengths since many address and data lines will only need to span across each bank
array individually.
Supply voltage ( V ): For decades, supply voltage ( V or V dd ) has dropped steadily with each
technology generation [ 113 ]. Because of its direct quadratic influence on dynamic power, this
has amazing leverage on power-aware design.
Activity factor ( A ): The activity factor is a fraction between 0 and 1 that refers to how
often wires actually transition from 0 to 1 or 1 to 0. While the clock signal obviously switches
at its full frequency, most other wires in the design have activity factors below 1. Strategies
such as clock gating are used to save energy by reducing activity factors during a hardware unit's
idle periods. In particular, the clock gating technique ANDs a unit's clock signal with a control
signal. When the control signal is 1, the unit will be clocked as expected. If the unit is known
to be unneeded for a cycle or more, the control signal can be set to 0, in which case the unit
will not be clocked; this can reduce the switching activity within it.
Clock frequency ( f ): The clock frequency has a fundamental and far-reaching impact on
power dissipation. Not only does clock frequency directly influence power dissipation, but it
also indirectly shapes power by its effect on supply voltage. Typically, maintaining higher clock
frequencies may require (in part) maintaining a higher supply voltage. Thus, the combined V 2 f
portion of the dynamic power equation has a cubic impact on power dissipation. Strategies such

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