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are user defined and set individually per program. Thus, the policy stops short of being fully
adaptive.
Yang et al. examine a 64KB DRI I-cache with SPEC95 [ 239 ]. With hand-selected
parameters per benchmark, the DRI cache can save up to 64% of the leakage power incurring
a performance penalty of 4% [ 239 ].
5.2.2 Cache Decay
Following the DRI cache, the idea of using the gated- V dd technique to turn off cache lines was
applied to data caches but at a much finer grain. The technique, called cache decay, turns a
cache line off if a pre-set number of cycles have elapsed since its last access [ 127 ]. 6 However,
turning off a cache line that is in active use incurs extra dynamic power re-fetching the line
from lower cache levels. Therefore, a central goal of cache decay is to accurately predict when a
cache line is no longer useful, or—as it is more commonly known—when a cache line is dead .
Cache decay is based on the fundamental generational behavior of cache lines. This
behavior was first discovered by Wood, Hill, and Kessler in their effort to support faster trace-
driven cache simulation [ 225 ]. At the time when the Wood et al. paper appeared, it was
prohibitive to use a long memory trace in a cache simulator—the limiting factor, of course,
being the capabilities of the machines of the time. One solution to this limitation is to skip
long stretches of the trace and simulate only some patches of the trace—or trace samples as they
are known. But what would the state of the (simulated) cache be after skipping a long stretch
of the trace? What cache lines would it contain?
The reason why the state of the cache is important is because the miss rate of unknown
references depends on it. Unknown references are the references that have not been encountered
before in the trace. It is unclear if they are actual cold misses for the cache or simply seen for
the first time because of part of the trace is skipped. Contrary to intuition—and much to their
surprise at the time—Wood et al. found that the miss rate of unknown references is much higher
(e.g., 0.4 rather than 0.02) than the steady-state miss rate of the cache. How can this be? The
answer lies in the generational behavior of the cache lines.
Generational behavior : The very high miss rate for the unknown references can be ex-
plained by a Renewal-theoretic model, which attributes to the cache lines a particular genera-
tional behavior . In simple terms, cache lines exist in “generations.” A generation begins when a
cache line is brought into the cache after a miss (see Figure 5.4). Immediately after the miss, a
flurry of access activity ensues. While the cache line is being accessed, it is in its live time .At
some point, the accesses cease and the cache line sits idle waiting to be evicted to make room for
a new line. The time spent in this state is called the dead time . The fundamental characteristic of
the generational behavior of cache lines, the reason why most of the cache is “empty” of useful
6 Adaptive and compiler-assisted cache decay variants were also proposed in [ 127 ].
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