Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 135

To understand the basic mechanisms for leakage reduction we have to take a closer look
at the formulas describing leakage current. We base our discussion on the Berkeley Predictive
Model (BSIM3V3.2) formula for subthreshold leakage [ 143 ] (which is also the starting point
for the simplified Butts and Sohi models [ 41 ] discussed in Chapter 2). The formula describing
the subthreshold leakage current, I Dsub ,is:

I s0 1

t e

e − V ds

V gs − V T − V off

= − .

I Dsub

v n · v

t

Here, V ds is the voltage bias across the drain and the source and V gs is the voltage bias
across the gate and source terminal. V off is an empirically determined BSIM model parameter
and q ) is a physical parameter called thermal voltage 1 which is proportional to the

temperature, T .Theterm n encapsulates various device constants, while the term I s0 depends
on the transistor geometry (in particular, the aspect ratio of the transistor, W

v v = /

t ( kT t

/ L ).

Immediately, this equation shows the dependence of leakage to W / L ,andits exponential

dependence to V ds , V gs , V T ,and T .

W L , transistor geometry : Leakage grows with the aspect ratio of a transistor and with

its size. Butts and Sohi use simplified models that encapsulate transistor geometry in
the k design parameter. They point out that very small transistors such as those found in
SRAMs can leak much less than sized-for-performance logic gate transistors. Tran-
sistor sizing is primarily a circuit-level concern and it will not preoccupy us at the
architecture level.

/

V ds , voltage differential between the drain and the source : This is probably the most
important parameter concerning the architectural techniques developed for leakage.
Two important leakage-control techniques that are based on reducing V ds are the
transistor stacking technique 2 and the drowsy technique— a.k.a. dynamic voltage scaling
(DVS) for leakage [ 77 ]. Both these techniques rely on the (1 e ( − V ds / V t ) ) factor of

the subthreshold leakage equation. This factor is approximately 1 with a large V ds
(i.e., V ds

−

t ) but falls off rapidly as V ds is reduced. Architectural
techniques based on transistor stacking—in particular, a stacking technique called
gated V dd [ 184 ]—and on the drowsy technique form the bulk of the work described in
this chapter. The former are presented in Section 5.2 and the latter in Section 5.3.

= V dd and V dd v

1 For the thermal voltage equation, k is Boltzmann's constant and q is the magnitude of the electron's charge. At
room temperature ( T 300 K), the thermal voltage is about 26 mV.

2 The stacking effect itself is also partially due to a change in the V T . This chance is dynamic and is caused by a
slight reverse bias induced by the top (off) transistor on the bottom (off) transistor.

=