Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 131

CHAPTER 5
Managing Static (Leakage) Power
Static power consumption has grown to a significant portion of total power consumption in
recent years. In CMOS technology, static power consumption is due to the imperfect nature
of transistors which “leak” current—thereby constantly consuming power—even when they are
not switching. The advent of this form of static power, called leakage power , was forecasted
early on [ 32 , 136 ], giving architects the opportunity to propose techniques to address it. Such
techniques are the focus of this chapter.
Considerable work to reduce leakage power consumption is taking place at the process
level [ 31 ]. In fact, process solutions such as the high-k dielectric materials in Intel's 45 nm
process technology, are already employed. Addressing the problem at the architectural level is,
however, indispensable because architectural techniques can be used orthogonally to process
technology solutions. The importance of architectural techniques is magnified by the exponential
dependence of leakage power to various operating parameters such as supply voltage ( V dd ),
temperature ( T ), and threshold voltage ( V T ). Exponential dependence implies that a leakage-
reduction solution that works well at some specific operating conditions may not be enough—
the problem is bound to reappear with the same intensity as before but at higher temperatures
or lower voltages.
Undeniably, the most fruitful ground for developing leakage-reduction techniques at the
architectural level has been the cache hierarchy. The large number of transistors in the on-chip
memory largely justifies the effort (or obsession) even though these transistors are not the
most “leaky”—that distinction goes to the high-speed logic transistors [ 41 ]. In addition, the
regularity of design and the access properties of the memory system have made it an excellent
target for developing high-level policies to fight leakage. Most of the architectural techniques
presented in this chapter, therefore, target caches or memory structures.
Chapter structure : The presentation of techniques in this chapter is structured according
to the type of low-level leakage-reduction mechanism employed (Table 5.1). Architectural
techniques inherit similar characteristics according to the physical quantity that is manipu-
lated by their low-level, leakage-reduction mechanism. Here, we concentrate on three ma-
jor low-level mechanisms (shown in Table 5.1). The first two, the stacking effect and the