Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 121

below has bandwidth, rather than power, as its main objective for optimization. Our approach
for presenting this work is to cluster the proposed techniques into two groups: (i) specialized
techniques to reduce switching in address busses—the low hanging fruit in this case—and
(ii) more general techniques applicable to both data and address buses.
4.12.1 Address Buses
Early work on bus encoding focused on address busses aiming to exploit their regular sequential
and stride behavior. One of the first encoding proposals, although not specifically for reducing
power consumption, is Dynamic Base Register Caching by Farrens and Park [ 75 ]. They show
that high-order address lines exhibit significant temporal and spatial locality and in most cases
transmit only redundant information. In their Dynamic Base Register Caching scheme, each
address is transmitted in two components: a high-order component (called base) and a low-
order component (called offset). The goal is to transmit mainly the low-order components that
change frequently, and only rarely the high-order components.
Low-order components are transmitted directly from processor to memory at all cases,
while high-order components are stored in a set of base registers located in both the processor
and in the memory. When the processor issues a new address, a search is performed in the set
of the base registers on the processor side. The goal is to find a register whose context matches
the high-order portion of the issued address. The set of registers is organized as a cache. On
a hit, the index to the cache entry is sent to memory, instead of the high-order portion itself.
When memory receives such an index, it extracts the high-order component of the address
from its own set of base registers. To formulate a complete address, the indexed base register
and ensuing offset are concatenated.
If the high-order component of an address is not found in one of the processor's base
registers, a fault occurs. One of the base registers at the processor side is immediately replaced
with the new high-order component. The memory is informed of this fault by the transmission
of a reserved index. The update process ends when the processor sends the corresponding
base register to memory. The authors examined both fully associative (LRU replacement) and
direct-mapped caches for the based register set.
The work of Farrens and Park is about I/O bandwidth rather than power consumption—
in 1991 performance was far more important than power. Not surprisingly, not much attention
is paid to the fact that what matters in bus switching is whether bus lines change value from
one cycle to the next. Thus, even if the high-order component was transmitted all the time, it
would not affect power consumption much since it would remain the same for most consecutive
addresses. Nevertheless, Farrens and Park exposed an important property of address busses.
Bona fide low-power approaches for address busses were proposed by Owens et al. [ 176 ]
and Benini et al. [ 27 ]. Both schemes are based on the sequentiality of the addresses as they