Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 120

Aragon et al. examine a range of throttling mechanisms: fetch throttling, decode throttling,
and selection-logic throttling [ 16 ]. As throttling is performed deeper in the pipeline, its impact
on execution is diminished. Thus, fetch throttling—at the start of the pipeline—is the most
aggressive in disrupting execution, starving the whole pipeline from instructions, while decode
or selection-logic throttling—deeper in the pipeline—are progressively less aggressive. This is
exploited in relation to branch confidence: the lower the confidence of a branch prediction the
more aggressively the pipeline is throttled. The overall technique is called selective throttling .
Pipeline gating, being an all-or-nothing mechanism, is much more sensitive to the
quality of the confidence estimator. This is due to the severe impact on performance when the
confidence estimation is wrong. Selective throttling, on the other hand, is better able to balance
confidence estimation with performance impact and power savings, yielding a better EDP for
representative SPEC 2000 and SPEC 95 benchmarks [ 16 ].
4.12 VALUE-DEPENDENT SWITCHING ACTIVITY:
BUS ENCODINGS
We conclude our classification of excess switching activity with an activity type appearing at a
low level, at the circuit or wire level. It is well known that switching activity in combinatorial and
sequential circuits varies with the inputs. For example, an adder exhibits different switching
activity depending on the numbers it adds. This raises the possibility of finding a different
encoding for the inputs that would lower the switching activity in typical operation. Although
it is standard practice in industry to test various encodings of data locally available at ciruit level
(e.g., using negated inputs) to see which one minimizes switching, here, we are concerned with
higher-level data encodings rooted on architectural properties. As such, most of the published
work in the area concerns data encodings for buses.
There are strong incentives to use data encoding on buses. First, buses consume a
significant amount of the total processor power so it pays to optimize their power consumption
as much as possible. Second, there are only two major factors that drive the power consumption
of a bus: the average number of signal transitions on its wires, and the capacitance of its wires.
Wire capacitance is mainly a circuit/device level issue and there are solutions to address it at
that level; it does not depend on the data carried on the bus (except for cross talk) .Butthe
number of signal transitions on the bus does depend on the data carried on the bus and this can
be dealt effectively via data encoding.
For off-chip busses, the benefits of encoding are even greater since their capacitive load
is orders of magnitude larger than that of internal buses [ 53 ]; thus, significant power can be
saved during off-chip transmission by encoding alone. In addition, reducing switching activity
can be thought of, not only as a way to decrease power consumption, but also as a way to
increase the apparent bandwidth of a bus or the I/O pins. In fact, some of the work we discuss