Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 105

Ordinary Set-Associative Cache:

Address: tag index b-offset

DATA DATA DATA DATA

Reactive-Associative Cache (Selective Direct-Mapping + way prediction):

Probe0: access predicted direct-mapped,

Probe1: Probe0 was mispredicted;
correct way number is taken from tag compare

or displaced at a predicted way number

Address: tag dm index b-offset tag dm index b-offset

DATA DATA

Instruction-based

predictor
predicted way number

DATA DATA

prediction: direct-mapped
or displaced?

DATA DATA

DATA DATA

tag compare

encoder

TIME

FIGURE 4.28: Reactive-associative cache and selective direct-mapping (with way prediction). The
reactive-associative cache maintains the parallel tag banks of a set-associative organization (top diagram)
but combines the data banks into one direct mapped bank (bottom diagrams).

position; otherwise it is in its direct-mapped position. If the cache line is conflicting, further
predicting where it was displaced (way-prediction) is simply an additional bonus. Any other
technique such as phased or sequential access could also be used instead. Because way prediction
only has to be used on the conflicting, displaced cache lines it is relatively an easier task.
Figure 4.28 shows how SDM works in conjunction with way prediction. The first probe
(Figure 4.28, bottom left) is guided by an instruction-based prediction mechanism (see also Fig-
ure 4.30 which gives an overview of the prediction schemes). The predictor either directs the first
probe to use the dm field of the address for the direct-mapped access or supplies a way prediction
for the set-associative access. 10 If, according to the tag comparison, the first probe fails, a second
probe accesses the data in its correct position, which is encoded from the tag comparison results.

10 The way-prediction can be supplied by any type of predictor. Powell et al. use a simple history-based predictor
indexed by an early approximation of the address. This approximation is derived as the contents of the source
address register XOR'ed with any immediate offset found in the corresponding instruction.