Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 102

Step 0

WAY
Predictor

DATA DATA DATA DATA

Step 1

Step 2 Compare

MUX

Step 3

DATA DATA DATA DATA

Step 1

Step 2 Compare

MUX

Step 3

FIGURE 4.26: Way prediction: Choose a way and access tag and data. In case of mismatch, access all
the rest of the ways in a second phase for the access.

low-power as the main goal. The general scheme, called way prediction , is depicted in
Figure 4.26. A separate prediction structure is employed to hold MRU information: for each
cache set a bit map points the MRU way with a set bit. This predictor structure is accessed
prior to the cache using the requested address (or parts thereof) and provides the prediction of
where the requested data are likely to be found.
Initially, only the predicted way (both tag and data arrays) is accessed. Tag comparison
determines a hit or a miss for the predicted way. In the case of a miss the remaining ways are
accessed in parallel, as in a normal set-associative cache, to determine whether the requested
data exist in a non-MRU position. This is a departure from the Kessler et al. scheme, where the
remaining ways are searched sequentially and not in parallel. The MRU predictor is updated