Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 90

Deactivated Ways

DATA DATA DATA DATA

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MUX

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FIGURE 4.18: Selective Cache Way: use smaller associativity. Shaded parts consume power on an
access. Deactivation mechanism not shown.

in a way that does not compromise the performance of the full-blown configuration. Unlike
intrusive approaches that could result in decreased clock speed or increased cache latency (in
cycles), the proposal for selective cache ways does not require anything that is not already there.
Large caches are partitioned into multiple subarrays for performance. This is a design time
partitioning, distinctly different from the dynamic (repeater-based) partitioning mentioned so
far. The goal of having smaller sub-arrays in the first place is to break the bit-lines and wordlines
into smaller segments to avoid the excessive delays of long wires. The geometry of the sub-arrays
is chosen in such a way as to equalize the delay of their bit-line and wordline segments. Given
this partitioning, the ways in a set-associative cache typically comprise one or more independent
sub-arrays. This, in turn, allows complete control over individual cache ways. Unneeded ways
can be disabled with little impact on the operation of the rest of the cache.
Disabling a cache way means that its data array simply does not react to cache accesses:
its bit-lines are not precharged, its wordlines are not activated, and its sense amplifiers are
prevented from firing. The tags of a disabled way, however, remain active. Figure 4.18 shows
a block diagram of a 4-way cache where two of its ways have been disabled. The output
multiplexor must be configured accordingly to ignore disabled ways.
Disabling a cache way brings up the question of what happens to its data—especially,
its modified (dirty) data. A low-power cache architecture cannot exclude a write-back policy,
therefore, dirty data are bound to exist in this case. One solution would be to flush the disabled
way and write back all its dirty data to memory. This, however, is the expensive solution. The
solution adopted in selective cache ways pushes the responsibility (and the complexity) to the
cache controller. Data in a disabled way can be accessed by briefly reinstating it into active
status. This happens in two situations. First, when a coherence request needs data from a
disabled way; second, when there is a hit in a disabled way. Both cases are detected by the cache