TIMING ANALYSIS FOR A COMBINATIONAL STAGE - Timing - page 90

or in opposite directions 5 . The second and third lines correspond to the cases
where there is no overlap in the switching windows.
Since are all dependent on the value of
(under‚ for example‚ a model)‚ the values of and
also depend on However‚ an examination of this table shows that
is itself dependent on the values of and
To break this cyclic dependency‚ iterative approaches are often employed.
The technique proposed in [Sap99‚ Sap00] provides a method that determines
worst-case bounds on the number of iterations required for convergence. Other
significant efforts in this direction include [Zho03]‚ which shows the problem
formulation in the context of a solution on a lattice‚ [TB03] that attempts to
remove the need for iterations‚ and [ARP00]‚ which employs this method in
the context of a full static timing analysis for a circuit with multiple stages of
logic.
In developing the concept of timing windows‚ three factors come into play:
Spatial neighborhood is clearly vital‚ since adjacency between nets is required
for any capacitive coupling.

and

Temporal aspects come into play since the timing window‚ described in terms
of the earliest and latest allowable switching times‚ must overlap in order to
excite a simultaneous switching scenario corresponding to the maximum or
minimum possible delay. If such overlap is not possible‚ then the maximum
and minimum delay computations must be suitably adjusted.

Functional issues correspond to Boolean relationships between the signals on
adjacent wires‚ and are also important. Even though the sum of the delays
on a path may predict temporal adjacency‚ the Boolean relationships in the
circuit may not permit the signals to switch simultaneously. The importance
of this lies in the fact that timing windows are often computed rapidly using
a static timing analyzer (which will be described in detail in Chapter 5)‚
which is blind to the logical relationships in a circuit; and simply sums up
the delays of gates on a path to find the maximum (or minimum) delay.
Techniques such as [KSV96‚ CK99‚ ABP01] have been proposed to address
the problem of integrating temporal and functional dependencies.
Therefore‚ timing window computations are vital to determining the effects
of crosstalk on timing. Most approaches define timing windows in terms of an