Civil Engineering Reference
In-Depth Information
From relations (4.8)-(4.12)‚ it is easy to see that for an RC line‚ the reduction
will always be realizable.
4.4.3 Effective capacitance computations
The use of the O'Brien-Savarino reduction to compute the gate delay still re-
quires the calibration of the delay of each gate with respect to the four pa-
rameters‚ and so that a four-dimensional look-up table must be
created for the gate delay. With points along each axis‚ this amounts to a
table with entries‚ clearly worse than the entries required for a purely
capacitive load. Even if curve-fitted formulae were to be used‚ the complexity
with four parameters would be much worse than with just two. The effective
capacitance‚ finds an equivalent capacitance that can be used to replace
the model‚ so that the delay characterization could continue to be performed
over two parameters.
The essence of the calculations lies in creating a model that draws the
same average current from a source as the model above‚ up to the 50%
delay time point. In order to achieve this‚ the gate output must be modeled by
an equivalent representation. Early efforts [QPP94] used a voltage source to
model the gate output‚ but it was later found [DMP96] that a Thevenin model
[NR00] with a voltage source and a resistor is more effective
3
.
