Civil Engineering Reference
In-Depth Information
the longest path problem must now be solved on a directed graph; this is well
known to be solvable in polynomial time [CLR90].
However‚ there may well be transistors that are not on the LRP that are
on in the worst case. To motivate the intuition for this‚ consider the graph
shown in Figure 4.5. Assume that the LRP between the output node and
ground through d has been found to be d‚ e. If‚ for example‚ transistor a is
also on‚ then the capacitance that must be driven by the resistors on d and e is
increased. Assuming the Elmore delay fidelity argument‚ the worst case delay
scenario corresponds to the case when the downstream capacitances are chosen
in such a way as to maximize the Elmore delay. Essentially‚ this implies that the
edges should be chosen in the following order: first‚ maximize the downstream
capacitance at the output node by setting the appropriate transistors to “on‚”
and then move along the LRP towards the ground node‚ each time setting
transistors to “on” to maximizing the downstream capacitance at that node‚
subject to the assignments already made.
In this specific case‚ at node we may set transistors and b to be
“on.” Next‚ moving to node we may set transistor f to be on. The worst
case assignment then corresponds to the case where the darkened edges in the
figure correspond to the on transistors. A more accurate calculator may now be
used for the delay computation from the input of transistor d to the output
This procedure does not incorporate the effects of correlations between the
inputs of a gate; one procedure that considers the case where the same signal
may drive multiple pins of a gate is described in [DY96].
4.4
EFFECTIVE CAPACITANCE: DELAYS UNDER RC LOADS
4.4.1
Motivation
The lumped capacitance model for interconnects is only accurate when the
driver resistance overwhelms the wire resistance; when the two are comparable‚
such a model could have significant errors. In particular‚ the phenomenon of
“resistive shielding” causes the delay at the driver output (referred to as the
driving point)
to be equivalent to a situation where it drives a lumped load that
is less than the total capacitance of the interconnect‚ as shown in Figure 4.6. In
effect‚ the interconnect resistance shields a part of the total capacitance from
the driving point. In this section‚ we will examine techniques that may be
used to derive a value for the
effective capacitance
at the driving point. Such a
capacitive model is particularly useful since it implies that cells may continue
to be characterized in terms of a load capacitance as in Section 4.3 even in the
domain where interconnect resistance is a dominant factor. The difference is
that the load capacitance is no longer the total capacitance driven by the gate‚
but a smaller value corresponding to the effective capacitance.
As stated earlier‚ the parasitics that are associated with MOS transistors‚
particularly the transistor resistance‚ show significant nonlinearities‚ while the
wire parasitics are linear. To take advantage of this‚ many timing analyzers
process a logic stage in two steps:
