TIMING ANALYSIS FOR A COMBINATIONAL STAGE - Timing - page 70

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TIMING ANALYSIS FOR A
COMBINATIONAL STAGE

4.1 INTRODUCTION

In Chapter 3‚ several techniques for the analysis of linear systems‚ such as
interconnect systems‚ were presented. In this chapter‚ we will first consider the
problem of analyzing the delay of a stage of combinational logic‚ consisting of a
logic gate and the interconnect wires driven by it‚ and then extend it to handle
coupled interconnect systems. This is a mixed linear / nonlinear system‚ since
the interconnect consists of purely linear elements‚ while the logic gate models
involve significant nonlinearities.

A simple way to address this problem is to approximate the nonlinear el-
ements using linear models. In this case‚ the drain-to-source resistance of a
transistor can be represented by a linear resistor. Under such a model‚ the the-
ory from Chapter 3 may be used to solve the resulting linear system. However‚
the accuracy of this method will be limited since real-life transistor models
show strong nonlinearities.

This chapter will present techniques for finding the delay of a stage of combi-
national logic‚ including both the nonlinear drivers and the linear interconnects.
We will begin our presentation under the assumption that the wires show no
capacitive coupling‚ and then extend the discussion to consider coupled inter-
connects.