Civil Engineering Reference
In-Depth Information
[FF98]
R. W. Freund and P. Feldmann. Reduced-order modeling of large
linear passive multi-terminal circuits using matrix-Padé approxi-
mation. In
Proceedings of Design‚ Automation and Test in Europe
Conference‚
pages 530-537‚ 1998.
[Fis90]
J. P. Fishburn. Clock skew optimization.
IEEE Transactions on
Computers‚
39(7):945-951‚ July 1990.
[FK82]
A. L. Fisher and H. T. Kung. Synchronizing large systolic arrays.
In
Proceedings of the SPIE‚
volume 341‚ pages 44-52‚ May 1982.
[Fre99]
R. W. Freund. Passive reduced order models for interconnect
simulation and their computation via Krylov subspace algorithms.
In
Proceedings of the ACM/IEEE Design Automation Conference‚
pages 195-200‚ 1999.
[Fri95]
E. G. Friedman‚ editor.
Clock distribution networks in VLSI cir-
cuits and systems.
IEEE Press‚ New York‚ NY‚ 1995.
[GARP98]
P. D. Gross‚ R. Arunachalam‚ K. Rajagopal‚ and L. T. Pileggi.
Determination of worst-case aggressor alignment for delay calcula-
tion. In
Proceedings of the IEEE/ACM International Conference
on Computer-Aided Design‚
pages 212-219‚ 1998.
K. Gala‚ D. Blaauw‚ J. Wang‚ V. Zolotov‚ and M. Zhao. In-
ductance 101: Analysis and design issues. In
Proceedings of the
ACM/IEEE Design Automation Conference‚
pages 329-334‚ 2001.
[Geb93]
C. H. Gebotys. Throughput optimized architectural synthesis.
IEEE Transactions on VLSI Systems‚
1(3):254-261‚ 1993.
[GLC94]
C. T. Gray‚ W. Liu‚ and R. K. Cavin‚ III.
Wave Pipelining: The-
ory and CMOS Implementation.
Kluwer Academic Publishers‚
Boston‚ MA‚ 1994.
[GS99]
E. Goldberg and A. Saldanha. Timing analysis with implicitly
specified false paths. In
Workshop Notes‚ International Workshop
on Timing Issues in the Specification and Synthesis of Digital Sys-
tems‚
pages 157-164‚ 1999.
[GS03]
B. Goplen and S. S. Sapatnekar. Efficient thermal placement
of standard cells in 3d ic?s using a force directed approach.
In
Proceedings of the IEEE/ACM International Conference on
Computer-Aided Design‚
pages 86-89‚ 2003.
[GTP97]
R. Gupta‚ B. Tutuianu‚ and L. T. Pileggi. The Elmore delay as a
bound for RC trees with generalized input signals.
IEEE Transac-
tions on Computer-Aided Design of Integrated Circuits and Sys-
tems‚
16(1):95-104‚ January 1997.
