Civil Engineering Reference
In-Depth Information
optimization of custom circuits using a static-timing formulation.
In Proceedings of the ACM/IEEE Design Automation Conference‚
pages 452-459‚ 1999.
[CGB01]
L.-C. Chen‚ S. K. Gupta‚ and M. A. Breuer. A new gate delay
model for simultaneous switching and its applications. In Pro-
ceedings of the ACM/IEEE Design Automation Conference‚ pages
289-294‚ 2001.
A. R. Conn‚ N. I. M. Gould‚ and P. L. Toint. LANCELOT: A
Fortran package for large-scale nonlinear optimization (Release
A). Springer-Verlag‚ Heidelberg‚ Germany‚ 1992.
[CGT92]
J.-H. Chern‚ J. Huang‚ L. Arledge‚ P.-C. Li‚ and P. Yang. Multi-
level metal capacitance models for CAD design synthesis systems.
IEEE Electron Device Letters‚ 13(1):32-34‚ January 1992.
[CHH92]
T. H. Chao‚ Y. C. Hsu‚ and J. M. Ho. Zero-skew clock net routing.
In Proceedings of the ACM/IEEE Design Automation Conference‚
pages 518-523‚ 1992.
J. Cong‚ L. He‚ C. K. Koh‚ and P. H. Madden. Performance
optimization of VLSI interconnect layout. Integration: The VLSI
Journal‚ 21(1-2):1-94‚ November 1996.
[CHKM96]
[CHNR93]
E. Chiprout‚ H. Heeb‚ M. S. Nakhla‚ and A. E. Ruehli. Simu-
lating 3-D retarded interconnect models using complex frequency
hopping (CFH). In Proceedings of the IEEE/ACM International
Conference on Computer-Aided Design‚ pages 66-72‚ 1993.
M. A. Cirit. Transistor sizing in CMOS circuits. In Proceedings of
the 24th ACM/IEEE Design Automation Conference‚ pages 121-
124‚ June 1987.
[Cir87]
[CK89]
P. K. Chan and K. Karplus. Computing signal delay in general
RC networks by tree/link partitioning. In Proceedings of the 26th
ACM/IEEE Design Automation Conference‚ pages 485-490‚ July
1989.
[CK91]
H. Y. Chen and S. M. Kang. iCOACH: A circuit optimization
aid for CMOS high-performance circuits. Integration‚ the VLSI
Journal‚ 10(2):185-212‚ January 1991.
[CK99]
P. Chen and K. Keutzer. Towards true crosstalk noise analy-
sis. In Proceedings of the IEEE/ACM International Conference
on Computer-Aided Design‚ pages 139-144‚ 1999.
Y. Cheng and S. M. Kang. A temperature-aware simulation
environment for reliable ULSI chip design. IEEE Transactions
[CK00]
Search WWH ::




Custom Search