Civil Engineering Reference
In-Depth Information
11
CONCLUSION
This topic has attempted to provide an overview of techniques that are used in
the timing analysis of digital circuits‚ with an exposition of methods used for
analyzing circuits at the gate/interconnect level‚ then at the level of a combi-
national stage‚ and finally as a larger sequential circuit. Methods for timing
optimization have been discussed‚ through transistor sizing and optimiza-
tion at the transistor level for combinational circuits‚ and through clock skew
scheduling and retiming for sequential circuits. A survey of statistical timing
methods has also been presented.
While this topic covers several of the basics of timing analysis‚ there are
several topics that it does not cover explicitly in great detail. However‚ the
foundation for understanding these issues is well laid out in our discussion.
Inductive effects
are becoming more prominent in nanometer technologies‚
particularly for long global wires such as those used for clock distribution‚
global busses‚ and power supply nets. There is a great deal of literature
available on the problem of extracting and analyzing inductive networks‚
and the material in Chapters 2 and 3 is very useful in understanding these
issues.
Timing-driven synthesis
Logic synthesis has traditionally been divided into
the technology-independent and technology-dependent phases. The latter
phase‚ which may perform technology mapping to a library‚ explicitly uses
timing information for synthesis. However‚ such timing estimates are closely
