Civil Engineering Reference
In-Depth Information
same time; this serves to reduce the peak current. The problem is modeled as
an integer linear program that minimizes the peak current. Each flip-flop may
have one of possible skew values. Correspondingly, for each flip-flop a set of
binary variables is used, of which exactly one variable is permitted to be 1, and
the skew of the flip-flop corresponds to this variable. The clock period of the
circuit imposes constraints on the possible skew value for each flip-flop, these
timing constraints are incorporated in the linear program. Experimental results
presented in [VHBM96] show a significant reduction in the ground bounce using
this technique. However, the use of an integer linear programming formulation
restricts the technique to system level design with few tens of modules. It is
possible that the application of heuristics to this technique may permit it to be
extended to larger designs, at the cost of sacrificing optimality.
A method for heuristic minimization of peak current by using clock skew is
presented in [VBBD96, BVBD97]. Experimental results on circuits with up to
550 flip-flops indicate an average reduction of about 30% in the peak current.
This method only minimizes the current peak directly caused by clock edges
using a genetic algorithm. The current waveform is approximated as a triangle
to allow efficient calculation of the total peak current in the circuit. The genetic
algorithm based solution results in a required skew at each flip-flop. Since clock
skew control for individual flip-flops is difficult, the flip-flops are clustered into
a user specified number of clusters, and each flip-flop in a cluster has the same
skew. A heuristic is used to attempt to cluster the flip-flops in such a way that
there is a minimal loss in optimality due to this simplification.
9.8
SUMMARY
The utility of deliberate skews for optimizing the performance of VLSI circuits
has been demonstrated‚ and algorithms for performing skew scheduling and
period minimization have been presented. Deliberate skews can also be used in
conjunction with other timing optimization strategies and for minimizing the
peak current in the supply network.
Until recently‚ there has been a great reluctance to alter the clock network
and attempt a nonzero-skew solution. However‚ recently‚ an increasing number
of designers have been willing to utilize skews for performance enhancement.
Small amounts of skews can easily be provided by making minor changes in the
sizes of the final buffers in the clock tree that feed the clock sinks‚ and altering
skews in this manner is a relatively painless manner in which the optimization
could be applied. For larger skew magnitudes‚ a more careful design of the clock
network is essential; for high-performance applications‚ the gains outweigh the
costs of this effort.
Notes
1. In subsequent generations of the processor‚ the regional clocks are provided by tree-
based structures [TDL03].
