Civil Engineering Reference
In-Depth Information
9.6
WAVE PIPELINING ISSUES
The treatment in [GLC94] provides an excellent illustration of the idea of wave
pipelining‚ and is summarized here. A conventional combinational circuit and
its associated timing are shown in Figure 9.14(a). The data flows out of the
input registers on the onset of the clock‚ and propagates through the logic‚
reaching the output registers in time for the onset of the next clock.
In contrast‚ in a wave pipelined system‚ the propagation time for the data
through the logic may be larger than the clock period. As an example‚ in
Figure 9.14(b)‚ the clocks at the input and output register are skewed. The
data that leaves the input registers reaches the output registers after more
than one clock period. During this time‚ the propagation of the second set of
data from the input registers has commenced at time Therefore‚ there
is a period of time when two different signals corresponding to two different
clock periods are flowing through the combinational logic‚ corresponding to two
“waves.” To ensure correct operation of the circuit‚ it is imperative to ensure
that the two waves do not collide. The advantage of wave pipelining over
conventional pipelining is that it may not require the use of as many registers‚
leading to potential savings in hardware and in the overhead of setup and hold
times at each register. Moreover‚ the overhead of clock distribution is also
reduced when the number of registers is reduced.
The critical issue in wave pipelining is to ensure that no two waves collide
during transmission. The work in [JC93] proposed an alteration of the clock
skew formulation of Fishburn [Fis90] to incorporate constraints that enforce
this requirement; these constraints are referred to as logic signal separation
constraints. Figure 9.15 shows two flip-flops‚
and
and a set of combinational
logic gates‚
and
Node is any predecessor gate of
such that flip-flop
