CLOCKING AND CLOCK SKEW OPTIMIZATION - Timing - page 180

allowable clock for this circuit has a period of 3 units. However‚ if a skew of
+ 1 unit is applied to the clock line to register L1‚ the circuit can operate under
a clock period of 2 units. This is possible because as shown in Figure 9.2‚ the
application of a skew of +1 unit delays the clock arrival at register L1 by one
unit‚ thus changing the required data arrival time to the new arrival time of the
first clock tick‚ which is 3 units (i.e.‚ the period of 2 unit delayed by +1 unit).
Under these circumstances‚ the actual data arrival time of 3 units does not
cause a timing violation‚ and the circuit is correctly clocked. A formal method
for determining the minimum clock period and the optimal skews was first
presented in the work by Fishburn [Fis90]‚ where the clock skew optimization
problem was formulated as a linear program that was solved to find the optimal
clock period.
A common misconception about changing clock skews is that it is believed
to be an “unsafe” optimization‚ in that a small change in the gate/interconnect
delays may cause a circuit with precariously small tolerances to malfunction. In
fact‚ this is not so; one can build in safety margins‚ as shown in Section 9.3‚ that
ensure that skewing errors do not disrupt circuit functionality. These margins
ensure that the circuit will operate in the presence of unintentional process-
dependent skew variations. In fact‚ introducing deliberate delays within the
clocking network has been a tactic that has long been used by designers [Wag88]
to squeeze extra performance from a chip‚ sometimes in a somewhat clandestine
manner. Only in the last few years has this idea become more “mainstream‚”