Civil Engineering Reference
In-Depth Information
include transistor sizing‚ dual optimization‚ and padding for short paths.
These are intended to provide a flavor for timing optimization and should not
be construed as a complete review of such methods. In addition to these‚
numerous methods for interconnect optimization using buffer insertion and wire
sizing have been proposed in the literature. Even more such techniques are on
the way: for instance‚ recent technologies have seen large increases in the gate
leakage (as opposed to the subthreshold leakage‚ addressed in Section 8.8)‚
which can be translated into a leakage/delay tradeoff problem by using dual
oxide thickness
values.
Notes
1. The current drive of a gate is controlled by the ratio of the channel width to channel
length‚ and if channel lengths are not uniform‚ this ratio can be considered as the size.
However‚ this may result in more complex functional forms for the area or power during
optimization.
2. This was subsequently extended to an RC tree model in iCONTRAST [SRVK93] to
model capacitors off the largest resistive path that must be charged/discharged.
3. In practice‚ when the effects of input transition times are considered under a more
accurate model‚ one may also have to consider a few stages downstream of the gate in which
the transistor lies.
4. It should be noted that Jiffytune predates VC99].
5. In a static CMOS gate‚ it is always possible to uniquely identify the source node and
the drain node. This may not be true in circuits with pass gates‚ which are not handled
in this work. The Jouppi rules [Jou87a]‚ for example‚ could be used to extend this work to
circuits with pass gates.
6. This refers to the leakage mechanism referred to as
subthreshold leakage‚
where the
nonideal nature of the transistor switch implies that it conducts a nonzero current in the
region where the gate-to-source voltage for an nmos transistor (or vice versa for a pmos
transistor) is below
in a regime where the transistor is supposedly off.
