Civil Engineering Reference
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hence for rise delay calculation‚ the nand gate is mapped to an inverter. In
a similar fashion‚ for the nor gate in Figure 8.7(b)‚ when the transition is at
input A‚ the gate is mapped to the primitive in Figure 8.6(d)‚ and when the
transition is at input B‚ the gate is mapped to the primitive in Figure 8.6(c).
Complex gates.
For more complex gates‚ an expanded set of primitives is
necessary. The set of primitives used to approximate complex CMOS gates is
shown in Figure 8.8.
Before explaining the procedure of delay modeling‚ we introduce the notion of
the
largest resistive path (LRP).
In the worst case switching scenario for a gate‚
there is exactly one path from the output node to the ground node for a fall
[rise] transition. This path may be formed by calculating equivalent widths for
