Civil Engineering Reference
In-Depth Information
We begin with an explanation of the timing model for an inverter‚ such as
the one shown in Figure 8.5; this model is generalized to complex gates in
subsequent sections. The aim is to be able to estimate delay as a function of
the pmos and nmos transistor widths‚ and the input transition time
and the output load capacitance‚ . Therefore‚ for an inverter‚
and form the set of characterization variables. These variables reflect the
set of variables that are generally considered to be important in defining the
delay of a gate in most models.
We attempted the use of several types of functions to achieve the desired
levels of accuracy. The general form of expression that provided consistently
good results for different gate types is as follows
Here‚ the are characterization variables‚ and the
C‚
and
are real constants‚ referred to collectively as
characterization constants.
The
parameter is set to either -1 or 1‚ depending on the variable‚ as will soon be
explained. The problem of characterization is that of determining appropriate
values for the characterization constants. We will show in Appendix C that the
use of this form of function implies that the circuit delay can be expressed as
a generalized posynomial function of the transistor widths.
Due to the curve-fitting nature of the characterization procedure (akin to
standard cell characterization)‚ it is not possible to ascribe direct physical
meanings to each of these terms. However‚ it can be seen that the fall de-
lay increases as and are increased‚ and decreases as is increased‚
implying that the value of for the first three variables must be 1‚ and that
for should be -1. Note that this is not as restrictive as the Elmore form
since‚ among other things‚ the provide an additional degree of freedom
that was not available for the Elmore delay form. A similar argument may be
made for the rise delay case.
Circuit simulations and curve-fitting.
A two-step methodology is adopted
to complete the characterization. In the first step‚ a number of circuit simula-
