Civil Engineering Reference
In-Depth Information
from
N.
Whenever an output node of gate is visited‚ TILOS examines the
largest resistive path between and the output node [between ground and
the output node] if the rise time [fall time] of
causes the timing failure at
N
.
This includes
The
critical transistor‚
i.e.‚ the transistor whose gate is on the critical path.
The
supporting transistors‚
i.e.‚ transistors along the largest resistive path
from the critical transistor to the power supply
or ground.
The
blocking transistors‚
i.e.‚ transistors along the highest resistance path
from the critical transistor to the logic gate output.
TILOS finds the sensitivity‚ which is the reduction in circuit delay per in-
crement of transistor size‚ for each critical‚ blocking and supporting transistor.
The size of the transistor with the greatest sensitivity is increased by multi-
plying it by a constant‚ BUMPSIZE‚ a user-settable parameter that defaults
to 1.5. Practically‚ it is observed that smaller values of 1.01‚ 1.05 or 1.1 can
provide better quality solutions‚ often without a very large CPU time penalty.
The above process is repeated until
all constraints are met‚ implying that a solution is found‚ or
the minimum delay state has been passed‚ and any increase in transistor
sizes would make it slower instead of faster‚ in which case TILOS cannot
find a solution.
The reason for increasing the transistor size by the factor BUMPSIZE‚ rather
than minimizing the delay along the critical path‚ is that such a minimization
would not necessarily optimize the delay of the circuit‚ since another path may
become critical instead; in such a case‚ the minimization would be overkill and
may involve an excessively large and unnecessary area overhead. Instead‚ the
delay along the current critical path is gradually reduced by this method‚ and
at the point at which another path becomes critical‚ its delay is reduced instead‚
and so on.
Note that since in each iteration‚ exactly one transistor size is changed‚ the
timing analysis method can employ incremental simulation techniques to up-
date delay information from the previous iteration. This substantially reduces
the amount of time spent by the algorithm in critical path detection.
The sensitivity calculation for the critical path can be carried out in a com-
putationally efficient manner. When a transistor
i
has its size bumped up by
the factor‚ BUMPSIZE‚ the delay of all gates on the path under consideration
remains unaltered‚ except for
the gate in which the transistor lies: since its driving power is increased‚ its
delay decreases.
the gate that drives this transistor: since it experiences a larger load‚ its
delay increases.
