Civil Engineering Reference
In-Depth Information
technology‚ and hence this is used as the initial solution. An STA step is then
carried out to check whether this initial solution satisfies the timing constraints
or not; if so‚ the solution has been found‚ and if not‚ an iterative procedure is
employed. In each iteration‚ the area is allowed to increase in such a way that
the largest impact is made on delay reduction. To reduce the circuit delay‚ the
area increase must necessarily be restricted to transistors on the critical path.
The ratio is a measure of the “bang per buck‚” and the transistor in a
gate on the critical path that provides the largest such ratio is upsized. The
STA step is repeated‚ and the iterations continue until the timing constraints
have been met.
The core of the algorithm requires a timing analysis and a sensitivity compu-
tation that calculates the delay change when a transistor size is perturbed; this
may be computed either using a sensitivity engine or by using finite differences
and multiple calls to the STA engine. In each iteration‚ since only a minor
change is made to the circuit (i.e., one transistor size is altered)‚ incremental
timing analysis techniques may be employed to reduce the overhead of timing
calculation.
8.3.1
The TILOS delay model
We examine delay modeling in TILOS at the transistor‚ gate and circuit levels.
At the transistor level‚ an RC model is used‚ with an approximated linear
source-to-drain resistance‚ and capacitances associated with the source‚ drain
and gate nodes. The resistance is inversely proportional to the transistor size‚
while the capacitances are directly proportional‚ with different constants of
proportionality for the gate node and the source/drain nodes.
At the gate level‚ TILOS operates in the following manner. For each tran-
sistor in a pullup or pulldown network of a complex gate‚ the largest resistive
path from the transistor to the gate output is computed‚ as well as the largest
resistive path from the transistor to a supply rail. Thus‚ for each transistor‚ the
network is transformed into an equivalent RC line corresponding to this path
2
‚
and the Elmore time constant for this RC line is computed. This Elmore delay
corresponds to the delay of the gate when the transition is caused by the tran-
sistor under consideration‚ and can be used to compute input-to-output pin
delays for all input pins in the gate. At the circuit level‚ the CPM technique‚
described in Section 5.2.1‚ is used to find the circuit delay, and gate delays are
computed on the fly as a gate is scheduled for processing.
8.3.2
Posynomial properties of the delay model
The circuit delay model above can be shown to fall into a class of real functions
known as
posynomials
that have excellent properties that can be exploited
during optimizations. A posynomial is afunction of a positive variable
that has the form
