Civil Engineering Reference
In-Depth Information
8
TRANSISTOR-LEVEL
COMBINATIONAL TIMING
OPTIMIZATION
8.1
INTRODUCTION
A typical digital integrated circuit consists of combinational logic blocks that
lie between memory elements that are clocked by system clock signals. For
such a circuit to obey long path and short path timing constraints‚ the delays
of the blocks should be adjusted so that they satisfy these constraints. As seen
in Chapter 7‚ this is easier for edge-triggered circuits than for level-clocked
circuits since for the former‚ the delay constraints can be applied separately
to each combinational block; for the latter‚ the existence of multicycle paths
makes the problem more involved‚ but it is still tractable. In our discussion
in this chapter‚ we will focus primarily on the timing optimization of edge-
triggered circuits since they are more widely used; extensions to level-clocked
circuits are primarily based on very similar methods.
For an edge-triggered circuit‚ the timing constraints dictate that valid signals
must be produced at each output latch of a combinational block before any
transition in the signal clocking the latch. In other words‚ the worst-case input-
output delay of each combinational stage must be restricted to be below a
certain specification. This may be achieved in various parts of the design cycle‚
but we will primarily focus on the role of back-end design tools here.
Timing optimization may be performed at various steps of the design cycle.
The technology-independent synthesis step [De 94] typically uses simple metrics
for timing: for instance‚ the delay of a circuit may be considered to be the num-
