Civil Engineering Reference
In-Depth Information
7.3.3
Timing constraints for level-clocked circuits
We now enumerate the set of timing constraints that dictate the correct opera-
tion of a level-clocked circuit. As before, the parameters and represent
the setup and hold times, respectively, of the latch, and we assume and
to be the minimum and maximum delays through each latch. As defined
earlier, for each pair of latches, and connected by a combinational path
the maximum and minimum path delays are denoted by
and
respectively.
The data input to each latch, has an associated arrival time that lies in
the range between the earliest time, and the latest time, Similarly,
the earliest and latest departure time of the data are denoted by and
respectively. All of these times are with respect to the local time zone of the
latch.
Due to the transparent nature of the latches, a signal can depart from latch
at any time during the active interval of the phase
i.e., between time
and
P.
In other words,
However, a signal cannot depart from a latch before it has arrived at that latch,
i.e.,
We can use the definitions of
and
to obtain the relations
The arrival time at a latch, of a signal departing from another latch,
connected by one or more purely combinational paths,
must satisfy the
following relations
where is the phase shift operator that translates a time in phase
into the local time in phase
In addition, the latest arrival time must be at least one setup time before
the falling edge of the clock, i.e., and the earliest arrival time
must occur no sooner than a hold time after the rising edge of the clock, i.e.,
