Civil Engineering Reference
In-Depth Information
A circuit in which all memory elements are level-clocked latches, is commonly
referred to as a level-clocked circuit, and a circuit composed of edge-triggered
FF's is called an edge-triggered circuit.
In our discussions, we will primarily deal with edge-triggered D flip-flops
and level-clocked D latches as representative memory elements. Other types of
storage elements that may be used include the RS latch, the JK flip-flop, and
the T flip-flop, but we will not address these specifically in our discussion. A
description of the transistor-level details of these registers is beyond the scope
of this topic, but we point out that various choices are available, and they
influence the number of transistors used, the number of clock signals to be
routed, and the area of and power dissipated by the chip [WE93].
7.2
CLOCKING DISCIPLINES: EDGE-TRIGGERED CIRCUITS
We will now overview the timing requirements for edge-triggered sequential
circuits, which consist of combinational blocks that lie between D flip-flops.
The basic parameters associated with a flip-flop can be summarized as follows:
The data input of the register, commonly referred to as the D input, must
receive incoming data at a time that is at least units before the onset
of the latching edge of the clock. The data will then be available at the
output node, Q, after the latching edge. The quantity,
is referred to
as the setup time of the flip-flop.
The input, D, must be kept stable for a time of units, where is
called the hold time, so that the data is allowed to be stored correctly in the
flip-flop.
Each latch has a delay between the time the data and clock are both available
at the input, and the time when it is latched; this is referred to as the clock-
to-Q delay,
In the edge-triggered scenario, let us consider two FF's,
and
connected
only by purely combinational paths. Over all such paths
let the largest
delay from FF
to FF
be
and the smallest delay be
Therefore,
for any path
with delay
it must be true that
