Civil Engineering Reference
In-Depth Information
7
TIMING ANALYSIS FOR
SEQUENTIAL CIRCUITS
7.1
INTRODUCTION
A general sequential circuit is a network of computational nodes (gates) and
memory elements (registers). The computational nodes may be conceptualized
as being clustered together in an acyclic network of gates that forms a com-
binational logic circuit. A cyclic path in the direction of signal propagation
is permitted in the sequential circuit only if it contains at least one register
1
.
In general, it is possible to represent any sequential circuit in terms of the
schematic shown in Figure 7.1, which has
I
inputs,
O
outputs and
M
registers.
The registers outputs feed into the combinational logic which, in turn, feeds
the register inputs. Thus, the combinational logic has
I + M
inputs and
O + M
outputs.
Pipelined systems , such as the one shown in Figure 7.2, are a special subset
of the class of general sequential circuits, and are commonly used in datapaths.
A pipelined system uses registers to capture the output of each logic stage at
the end of each clock period. Data proceeds through each combinational block,
or pipeline stage, until it reaches the end of the pipeline, with the registers
serving to isolate individual stages so that they may parallelly process data
corresponding to different data sets, which increases the data throughput rate
of the system. While many pipelines have no feedback, the definition of a
pipeline does not preclude the use of feedback, and algorithms for scheduling
data into a pipeline with feedback have been devised. Acyclic pipelines form an
