TIMING ANALYSIS FOR COMBINATIONAL CIRCUITS - Timing - page 103

in the library with the same functionality, but higher rise and fall delays. The
redistribution of slack plays a vital role in timing analysis, and various methods
for this purpose have been presented in, for example, [NBHY89, YS90, SSP02].
It should be noted that the critical path can also be found using the slack
information. The lowest slack at the primary output is -1, and by tracing back
from the primary output towards the primary inputs and following the path
with a slack of -1 yields the critical path of the circuit.
5.2.3 Extensions to more complex cases
For ease of exposition, the example in the previous section contained a number
of simplifying assumptions. The critical path method can work under more gen-
eral problem formulations, and a few of these that are commonly encountered
are listed below:
Nonzero arrival times at the primary inputs If the combinational block
is a part of a larger circuit, we may have nonzero rise/fall arrival times at the
primary inputs. If so, the CPM traversal can be carried out by simply using
these values instead of zero as the arrival times at the primary inputs. This
is particularly useful in characterizing blocks, and may be used to create
hierarchical models.
Minimum delay calculations When the gate delays are fixed, the method
described above can easily be adapted to find the minimum, instead of the
maximum delay from any input to any output. The only changes in the
procedure involve the manner in which an individual block is processed: the
earliest arrival time over all inputs is now added to the delay of the block to
find the earliest arrival time at its output.
Minmax delay calculations If the gate delay is specified in terms of an in-
terval, then the minimum and maximum arrival time intervals
can be propagated in a similar manner; again, these values may be main-
tained separately for the rising and falling output transitions. The values of
and can be computed on the fly while processing a gate, as will
be explained shortly.
Noninverting gates In the example above, all blocks are assumed to consist
of inverting gates, due to which a rising transition at the output is caused
by a falling transition at the input and vice versa. In case of a noninverting
gate/block, a simple adjustment may be made by realizing that the rise [fall]
transition at the output is effected by a rise [fall] transition at the input.
Generalized block delay models If the delay from input pin to output
pin of a blocks is and the values of are not all uniform for a block,
then the arrival time at the output can be computed as